eolas/Electronics_and_Hardware/Digital_circuits/Flip_flops.md
2022-12-12 07:30:05 +00:00

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logic-gates
binary
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clock

Flip-Flops

A flip-flop is a type of latch that is connected to a clock signal and which executes in time with the clock's pulse. (Sometimes "latch" and "flip-flop" are used interchangeably but technically a latch is flip-flop without a clock connection.)

JK Flip-Flop

The JK Flip-Flop (the letters are meaningless) is basically an SR latch in functionality. It has a "set" input (J) and a "reset" input (K) and Q and inverted-Q outputs.

Where it differs from the SR is that it the SR will change state just if the voltage is high (this, afterall, is all that a bit is) whereas for the JK to set it must receive a clock pulse and it will only set on the pulse.

In addition the JK Flip-Flop has a toggle function. When this is executed, whatever Q currently is will be flipped to its opposite value: 1 \rightarrow 0, 0 \rightarrow 1. The toggle executes when both J and K are set to high.

The possible state changes for the JK Flip-Flop are detailed below:

J K Clock Q state Operation
0 0 Pulse Maintain previous value Hold
0 1 Pulse 0 Reset
1 0 Pulse 1 Set
1 1 Pulse Inverse of previous value Toggle

A JK Flip-Flop can execute on either the positive or negative pulse. Below are the diagrams fora rising and falling pulse respectively:

// TODO diagram of JK Flipflop