From ee68154dd0c023090e74c421ad71b963915b5bf4 Mon Sep 17 00:00:00 2001 From: Thomas Bishop Date: Thu, 1 Dec 2022 18:41:18 +0000 Subject: [PATCH] Add more diagrams --- Electronics/Digital_Circuits/Half_adder_and_full_adder.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md index d7cdb29..fa13907 100644 --- a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md +++ b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md @@ -87,9 +87,11 @@ And the carry-out bit replicates the truth conditions of [AND](/Hardware/Logic_G It is therefore possible to implement a half-adder with just these two logic gates: +![](/img/half-adder-gates-three.png) + The digital circuit above has the same inputs and outputs as the half adder diagram above. - + ## Full adder @@ -126,4 +128,4 @@ The sume of HA1 ($0 + 0$) is passed in to the B input on HA2 and the $1$ is pass At this point we have completed the addition and have successfully added the three bits: $1$, $0$, and $0$ to get $1$ as ths sum. However we also have to account for the fact that the addition may result in its own carry-out bit. What if the inputs were $1, 1, 0$ for example? - +