diff --git a/Computer_Architecture/CPU/CPU_architecture.md b/Computer_Architecture/CPU/CPU_architecture.md
index 8abc750..332c488 100644
--- a/Computer_Architecture/CPU/CPU_architecture.md
+++ b/Computer_Architecture/CPU/CPU_architecture.md
@@ -1,7 +1,7 @@
 ---
 categories:
   - Computer Architecture
-tags: [CPU, electromagnetism]
+tags: [CPU, electromagnetism, clock]
 ---
 
 # CPU architecture
diff --git a/Electronics_and_Hardware/Digital_circuits/Clock_signals.md b/Electronics_and_Hardware/Digital_circuits/Clock_signals.md
index 905de01..fc19e24 100644
--- a/Electronics_and_Hardware/Digital_circuits/Clock_signals.md
+++ b/Electronics_and_Hardware/Digital_circuits/Clock_signals.md
@@ -3,11 +3,29 @@ categories:
   - Computer Architecture
   - Electronics
   - Hardware
-tags: [logic-gates, binary, memory]
+tags: [logic-gates, binary, memory, clock, electromagnetism]
 ---
 
 # Clock signals
 
-When using multiple [memory devices](/Electronics_and_Hardware/Digital_circuits/Latches.md) in a complex digital circuit we need a way to ensure that all the bits are set at the same time. In the examples so far of [adders](/Electronics_and_Hardware/Digital_circuits/Half_adder_and_full_adder.md) and [latches](/Electronics_and_Hardware/Digital_circuits/Latches.md)
+In the examples of digital circuits so far (i.e [adders](/Electronics_and_Hardware/Digital_circuits/Half_adder_and_full_adder.md) and [latches](/Electronics_and_Hardware/Digital_circuits/Latches.md)) everything happens in a single instant or over several repeated instances. This is because of how simple the circuits are. In the case of latches only a single bit is updated. And even with rippled adders they are just a series of 1-bit updaters in a chain.
+
+With more complex circuits that use multiple memory devices which store a series of bits at once, we need a way to ensure that the bits are set at the same time.
+
+We synchronize multiple circuit components with a **clock signal**.
+
+A clock signal alternates its voltage level from high to low on a regular cadence where it is high half the time and low the rest of the time. This gives the wave form a squared appearence.
+
+A single iteration of the volatage rising and falling is a **pulse**. A complete oscillation from low to high and back to low is a **cycle**. As with all [electromagnetic]() signals we measure the frequency of the wave in Hertz: cylcles per second. We also further distinguish the rising and falling edge of a pulse. Rising represents the signal passing from ground to its maximum voltage and falling is the reverse (the electrons moving from the voltage source to ground).
+
+The diagram below shows a pulse cycle of 2Hz.
 
 ![](/img/clock_pulses.png)
+
+## Linking components to the clock
+
+- All components that need to be synchronised are connected to the clock
+- State changes in the component occur only when a clock pulse occurs
+- Clock-driven components will typically trigger their state changes on either the rising edge or the falling edge of the pulse.
+- Components that trigger state changes on the rising pulse are **positive edge-triggered**
+- Components that trigger state changes on the falling pulse are **negative edge-triggered**