From 7f337fcf2ca2be1de002224037d7fffaeab3f282 Mon Sep 17 00:00:00 2001 From: tactonbishop Date: Tue, 29 Nov 2022 07:00:05 +0000 Subject: [PATCH 1/4] Last Sync: 2022-11-29 07:00:05 --- Electronics/Digital_Circuits/Half_adder_and_full_adder.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md index dd80faf..5d7b44b 100644 --- a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md +++ b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md @@ -49,7 +49,6 @@ The symbol for the half adder is displayed below It has two inputs and two ouputs: -| Input | Input | Output | Output | -| ---------------------------- | ----------------------------- | ----------- | ----------------- | | A | B | S | C_out | +| ---------------------------- | ----------------------------- | ----------- | ----------------- | | The first number to be added | The second number to be added | The sum bit | The carry-out bit | From 8dc50dfd9b64ae30e504cd6e13b8eb8f72c00a2d Mon Sep 17 00:00:00 2001 From: tactonbishop Date: Tue, 29 Nov 2022 07:30:04 +0000 Subject: [PATCH 2/4] Last Sync: 2022-11-29 07:30:04 --- .../Half_adder_and_full_adder.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md index 5d7b44b..34a3d15 100644 --- a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md +++ b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md @@ -35,20 +35,20 @@ From the previous example we can identified the following repeated actions: - For calculations of the form $1 + 0$ or $0 + 0$ there will be no carried digit - For calculations of the form $1 + 1$ there will be a carried digit -In the context of adders the digits are bits. We distinguish the **least significant bit** and **most significant bit**. The least significant bit is the right-most digit in the calculation. The most significant bit is the leftmost: - -// TODO: Add diagram highlighting least and most significant bits. +In the context of adders the digits are bits. We distinguish three core bits by their role in the calculation: the carry, the **least significant bit** and the **most significant bit**. The least significant bit is the right-most digit in the calculation. The most significant bit is the leftmost. The two types of adders are distinguished by which bits of the calculation they operate on. The half adder focuses on the least significant bit whereas the full adder focuses on the most significant bit. ## Half adder -The symbol for the half adder is displayed below - -// TODO: Add diagram of half adder - -It has two inputs and two ouputs: +The half adder receives two bits (A and B) which are to be added together.It outputs this value as the **sum bit**. If this value exceeds $1$, the sum bit will be $0$ and the **carry-out** ($c_{out}$) bit will be $1$. In cases where the sum bit does not exceed $1$ the carry-out bit will be $0$. | A | B | S | C_out | | ---------------------------- | ----------------------------- | ----------- | ----------------- | | The first number to be added | The second number to be added | The sum bit | The carry-out bit | + +The diagram below shows the circuit representation of a half-adder and an example calculation. This calculation matches the ones column of the earlier binary addition example: $0011 + 0010$. + +![](/img/half-adder-new.png) + +### Implementation with logic gates From 0e2a76e2c1e861297b717d61ca4d7455027b2522 Mon Sep 17 00:00:00 2001 From: tactonbishop Date: Tue, 29 Nov 2022 08:00:05 +0000 Subject: [PATCH 3/4] Last Sync: 2022-11-29 08:00:05 --- .../Half_adder_and_full_adder.md | 36 ++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-) diff --git a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md index 34a3d15..3061481 100644 --- a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md +++ b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md @@ -41,7 +41,7 @@ The two types of adders are distinguished by which bits of the calculation they ## Half adder -The half adder receives two bits (A and B) which are to be added together.It outputs this value as the **sum bit**. If this value exceeds $1$, the sum bit will be $0$ and the **carry-out** ($c_{out}$) bit will be $1$. In cases where the sum bit does not exceed $1$ the carry-out bit will be $0$. +The half adder receives two bits (A and B) which are to be added together. It outputs this value as the **sum bit**. If there is a bit to be carried to the next column in the binary calculation this will be output as the **carry-out** bit. | A | B | S | C_out | | ---------------------------- | ----------------------------- | ----------- | ----------------- | @@ -52,3 +52,37 @@ The diagram below shows the circuit representation of a half-adder and an exampl ![](/img/half-adder-new.png) ### Implementation with logic gates + +If we think about it, the possible inputs and outputs of a half adder are highly circumscribed: + +- If the sum exceeds $1$, the sum bit will be $0$ and the carry-out bit will be $1$ +- In all other cases the carry-out bit will be $0$. These other cases are when the sum bit is either $0$ or $1$, e.g: $1 + 0$ or $0 + 0$. + +We can represent this with a simple truth-table: + +| A | B | S | C_out | +| --- | --- | --- | ----- | +| 0 | 0 | 0 | 0 | +| 0 | 1 | 1 | 0 | +| 1 | 0 | 1 | 0 | +| 1 | 1 | 0 | 1 | + +We can see that the sum bit column replicates the truth-conditions of [XOR](/Hardware/Logic_Gates/Xor_gate.md): + +| P | Q | P V Q | +| --- | --- | ----- | +| T | T | F | +| T | F | T | +| F | T | T | +| F | F | F | + +And the carry-out bit replicates the truth conditions of [AND](/Hardware/Logic_Gates/And_gate.md): + +| P | Q | ~(P & Q) | +| --- | --- | -------- | +| T | T | F | +| T | F | F | +| F | T | F | +| F | F | T | + +It is therefore possible to implement a half-adder with just these two logic gates: From 29b0beddf2f49d3dd46ccc32d50bd587c09d29a8 Mon Sep 17 00:00:00 2001 From: tactonbishop Date: Wed, 30 Nov 2022 07:30:04 +0000 Subject: [PATCH 4/4] Last Sync: 2022-11-30 07:30:04 --- .../Digital_Circuits/Half_adder_and_full_adder.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md index 3061481..9821535 100644 --- a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md +++ b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md @@ -86,3 +86,13 @@ And the carry-out bit replicates the truth conditions of [AND](/Hardware/Logic_G | F | F | T | It is therefore possible to implement a half-adder with just these two logic gates: + +The digital circuit above has the same inputs and outputs as the half adder diagram above. + + + +## Full adder + +As the half adder only calculates the least significant bit, it is not sufficient by itself to complete a binary addition; it cannot account for movements in binary place value. To carry out full calculations it must be supplemented with the full adder. + +The full adder takes in three inputs and has two inputs. It is identical to the half-adder apart from the fact that one of its inputs is **carry-in**. This is obviously equivalent to the value that is designated as **carry-out** in a half adder