Autosave: 2023-01-02 09:30:05
This commit is contained in:
parent
cbb02197bb
commit
64e3b2d4bd
1 changed files with 15 additions and 26 deletions
|
@ -5,37 +5,26 @@ categories:
|
||||||
tags: [motherboard]
|
tags: [motherboard]
|
||||||
---
|
---
|
||||||
|
|
||||||
#
|
|
||||||
|
|
||||||
# Bus
|
# Bus
|
||||||
|
|
||||||
A bus is a communication system that transfers data between components inside a computer, or between computers.
|
A bus is a communication system that transfers data between components inside a computer, or between computers. **A bus can be thought of as a kind of pipeline that allows different components of the computer to communicate with each other.**
|
||||||
|
|
||||||
|
Note that the use of the word "bus" varies somewhat in points of emphasis. A bus can mean:
|
||||||
|
|
||||||
|
- The physical wires that make up the bus
|
||||||
|
- The logical communication channel that is established over those wires
|
||||||
|
- The collection of bits themselves that travel along the wires conceived as a single entity
|
||||||
|
|
||||||
## Main buses
|
## Main buses
|
||||||
|
|
||||||
### System bus
|
| Bus type | Description |
|
||||||
|
| ------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ |
|
||||||
The primary pathway between the CPU and [memory](/Computer_Architecture/Memory/Memory.md). It comprises the **data bus** that transfers data from the memory to the CPU and the **address bus** which transmits requests from the CPU to memory.
|
| System bus | The primary pathway between the CPU and [memory](/Computer_Architecture/Memory/Memory.md). It comprises the **data bus** that transfers data from the memory to the CPU and the **address bus** which transmits requests from the CPU to memory. |
|
||||||
|
| Internal bus | Connects local devices for example the harddisk to the CPU. |
|
||||||
### Internal bus
|
| External bus | Connects peripheral devices such as disks and printers to the [motherboard](/Electronics_and_Hardware/Motherboard.md) |
|
||||||
|
| Expansion bus | Allows expansion boards to access the CPU and memory. |
|
||||||
Connects local devices for example the harddisk to the CPU.
|
| Frontside bus | Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](Electronics_and_Hardware/Motherboard.md) devices. |
|
||||||
|
| Backside bus | Transfers secondary cache (L2 cache) data at faster speeds, allowing more efficient CPU operations |
|
||||||
### External bus
|
|
||||||
|
|
||||||
Connects peripheral devices such as disks and printers to the [motherboard](/Electronics_and_Hardware/Motherboard.md)
|
|
||||||
|
|
||||||
### Expansion bus
|
|
||||||
|
|
||||||
Allows expansion boards to access the CPU and memory.
|
|
||||||
|
|
||||||
### Frontside bus
|
|
||||||
|
|
||||||
Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](Electronics_and_Hardware/Motherboard.md) devices.
|
|
||||||
|
|
||||||
### Backside bus
|
|
||||||
|
|
||||||
Transfers secondary cache (L2 cache) data at faster speeds, allowing more efficient CPU operations
|
|
||||||
|
|
||||||
## Bus standards
|
## Bus standards
|
||||||
|
|
||||||
|
|
Loading…
Add table
Reference in a new issue