Last Sync: 2022-12-05 08:00:05
This commit is contained in:
tactonbishop
parent
28b4e336ec
commit
5d44900e70
7 changed files with 72 additions and 217 deletions
|
|
@ -79,12 +79,12 @@ We can see that the sum bit column replicates the truth-conditions of [XOR](/Har
|
||||||
|
|
||||||
And the carry-out bit replicates the truth conditions of [AND](/Hardware/Logic_Gates/And_gate.md):
|
And the carry-out bit replicates the truth conditions of [AND](/Hardware/Logic_Gates/And_gate.md):
|
||||||
|
|
||||||
| P | Q | ~(P & Q) |
|
| P | Q | P & Q |
|
||||||
| --- | --- | -------- |
|
| --- | --- | ----- |
|
||||||
| T | T | F |
|
| T | T | F |
|
||||||
| T | F | F |
|
| T | F | F |
|
||||||
| F | T | F |
|
| F | T | F |
|
||||||
| F | F | T |
|
| F | F | T |
|
||||||
|
|
||||||
It is therefore possible to implement a half-adder with just these two logic gates:
|
It is therefore possible to implement a half-adder with just these two logic gates:
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,61 +0,0 @@
|
||||||
---
|
|
||||||
categories:
|
|
||||||
- Computer Architecture
|
|
||||||
- Electronics
|
|
||||||
tags: [binary]
|
|
||||||
---
|
|
||||||
|
|
||||||
# Binary arithmetic with circuits
|
|
||||||
|
|
||||||
|
|
||||||
Now that we know how to add and multiply using binary numbers we can apply this knowledge to our previous understanding of circuits.
|
|
||||||
|
|
||||||
Our aim will to be have our inputs as the numbers that we will add or multiply on and our outputs as the product or sum.
|
|
||||||
|
|
||||||
## Half adder
|
|
||||||
|
|
||||||
Let's start with the most basic example:
|
|
||||||
|
|
||||||
*Half adder circuit*
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
This circuit has the following possible range of outputs, where A and B are the input switches and X and Y are the output signals. The logic gates (an `XOR` and an `AND` ) are equivalent to the add function.
|
|
||||||
|
|
||||||
````
|
|
||||||
A B X Y
|
|
||||||
_ _ _ _
|
|
||||||
|
|
||||||
0 0 0 0
|
|
||||||
0 1 0 1
|
|
||||||
1 0 0 1
|
|
||||||
1 1 1 1
|
|
||||||
````
|
|
||||||
|
|
||||||
We can see that if we treat A and B as single binary digits that could correspond to $2^1$ (either `0` or `1` ) , then the X and Y outputs can be viewed collectively to constitute the sum of A and B (we have put the denary equivalent in brackets)
|
|
||||||
|
|
||||||
````
|
|
||||||
A B X Y
|
|
||||||
_ _ _ _
|
|
||||||
|
|
||||||
0 0 0 0 0 + 0 = 00 [0]
|
|
||||||
0 1 0 1 0 + 1 = 01 [1]
|
|
||||||
1 0 0 1 1 + 0 = 01 [0]
|
|
||||||
1 1 1 1 1 + 1 = 10 [2]
|
|
||||||
````
|
|
||||||
|
|
||||||
This is called a half adder because it cannot go higher than $2^1$.
|
|
||||||
|
|
||||||
### Representing binary output as denary values
|
|
||||||
|
|
||||||
There are special output components that can represent the combination of binary inputs and logic gates as denary values. Here is an example using a **seven-segment display** :
|
|
||||||
|
|
||||||
|
|
||||||
[](/img/recalc_img.gif)
|
|
||||||
## Full adder
|
|
||||||
|
|
||||||
To represent numbers higher than the denary 2, we would need a carrying function so that we could represent numbers up to denary 3 and 4. The limit of a half adder is $2^1$.
|
|
||||||
|
|
||||||
We do this by adding another switch input:
|
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -1,45 +0,0 @@
|
||||||
---
|
|
||||||
categories:
|
|
||||||
- Computer Architecture
|
|
||||||
- Electronics
|
|
||||||
- Hardware
|
|
||||||
tags: [logic-gates]
|
|
||||||
---
|
|
||||||
|
|
||||||
# AND gate
|
|
||||||
|
|
||||||
Just as we can create `NOT` logic from a NAND gate, without the `AND` conditions, we can create a circuit that exemplifies the truth conditions of `AND` just by discluding those of those of `NOT`.
|
|
||||||
|
|
||||||
When we attach two NAND gates in sequence connected to two switches as input this creates the following binary conditions:
|
|
||||||
|
|
||||||
```
|
|
||||||
A B Output
|
|
||||||
_ _ _____
|
|
||||||
|
|
||||||
1 1 1 (1)
|
|
||||||
1 0 0 (2)
|
|
||||||
0 1 0 (3)
|
|
||||||
0 0 0 (4)
|
|
||||||
```
|
|
||||||
|
|
||||||
Which is identical to the truth table for `AND` :
|
|
||||||
|
|
||||||
```
|
|
||||||
p q p & q
|
|
||||||
_ _ _____
|
|
||||||
|
|
||||||
t t t (1)
|
|
||||||
t f f (2)
|
|
||||||
f t f (3)
|
|
||||||
f f f (4)
|
|
||||||
```
|
|
||||||
|
|
||||||
**An AND at 0 0 :**
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
**AND at 1 0 or 0 1 :**
|
|
||||||
|
|
||||||
|
|
||||||
**AND at 1 1**
|
|
||||||
|
|
||||||
|
|
@ -13,6 +13,72 @@ tags: [logic-gates, binary]
|
||||||
Logic gates are the basic building blocks of digital computing. **A logic gate is an electrical circuit that has one or more than one input and only one output.** The input controls the output and the logic determining which types of input (on/off) lead to specific outputs (on/off) is identical to the truth-conditions of the [Boolean connectives](/Logic/Truth-functional_connectives.md) specifiable in terms of [truth-tables](/Logic/Truth-tables.md).
|
Logic gates are the basic building blocks of digital computing. **A logic gate is an electrical circuit that has one or more than one input and only one output.** The input controls the output and the logic determining which types of input (on/off) lead to specific outputs (on/off) is identical to the truth-conditions of the [Boolean connectives](/Logic/Truth-functional_connectives.md) specifiable in terms of [truth-tables](/Logic/Truth-tables.md).
|
||||||
Physically, what 'travels through' the gates is electrical current and what constitutes the 'gate' is a [transistor](/Electronics/Digital_Circuits/Transistors.md) responding to the current. At the next level of abstraction it is bits that go into the gate and bits which come out: binary information that may be either 1 or 0.
|
Physically, what 'travels through' the gates is electrical current and what constitutes the 'gate' is a [transistor](/Electronics/Digital_Circuits/Transistors.md) responding to the current. At the next level of abstraction it is bits that go into the gate and bits which come out: binary information that may be either 1 or 0.
|
||||||
|
|
||||||
|
## AND gate
|
||||||
|
|
||||||
|
> The AND gate represents the truth conditions of the [conjunction](/Logic/Truth-functional_connectives.md#conjunction) truth functional connective
|
||||||
|
|
||||||
|
### Symbol
|
||||||
|
|
||||||
|
### Truth conditions
|
||||||
|
|
||||||
|
| P | Q | P & Q |
|
||||||
|
| --- | --- | ----- |
|
||||||
|
| T | T | T |
|
||||||
|
| T | F | F |
|
||||||
|
| F | T | F |
|
||||||
|
| F | F | F |
|
||||||
|
|
||||||
|
### Interactive circuit
|
||||||
|
|
||||||
|
## NAND gate
|
||||||
|
|
||||||
|
> The NAND gate inverts the truth conditions of AND.
|
||||||
|
|
||||||
|
### Symbol
|
||||||
|
|
||||||
|
### Truth conditions
|
||||||
|
|
||||||
|
| P | Q | ~(P & Q) |
|
||||||
|
| --- | --- | -------- |
|
||||||
|
| T | T | F |
|
||||||
|
| T | F | F |
|
||||||
|
| F | T | F |
|
||||||
|
| F | F | T |
|
||||||
|
|
||||||
|
NAND is a **universal logic gate**: equipped with just a NAND we can represent every other possible logical condition. In practice with circuits, it is more efficient to use specific dedicated gates (i.e OR, AND, NOT etc) for the other Boolean connectives but in principle the same output can be achieved through NANDs alone.
|
||||||
|
|
||||||
|
## OR gate
|
||||||
|
|
||||||
|
> The OR gate represents the truth conditions of the [disjunction](/Logic/Truth-functional_connectives.md#disjunction) truth functional connective
|
||||||
|
|
||||||
|
### Symbol
|
||||||
|
|
||||||
|
### Truth conditions
|
||||||
|
|
||||||
|
| P | Q | P v Q |
|
||||||
|
| --- | --- | ----- |
|
||||||
|
| T | T | T |
|
||||||
|
| T | F | T |
|
||||||
|
| F | T | T |
|
||||||
|
| F | F | F |
|
||||||
|
|
||||||
|
## XOR gate
|
||||||
|
|
||||||
|
> The OR gate represents the truth conditions of the exclusive OR
|
||||||
|
|
||||||
|
### Symbol
|
||||||
|
|
||||||
|
### Truth conditions
|
||||||
|
|
||||||
|
| P | Q | ~(P <> Q) |
|
||||||
|
| --- | --- | --------- |
|
||||||
|
| T | T | F |
|
||||||
|
| T | F | T |
|
||||||
|
| F | T | T |
|
||||||
|
| F | F | F |
|
||||||
|
|
||||||
|
### Interactive circuit
|
||||||
|
|
||||||
## References
|
## References
|
||||||
|
|
||||||
Scott, J. Clark. 2009. _But how do it know?: the basic principles of computers for everyone_. Self-published.
|
Scott, J. Clark. 2009. _But how do it know?: the basic principles of computers for everyone_. Self-published.
|
||||||
|
|
|
||||||
|
|
@ -1,56 +0,0 @@
|
||||||
---
|
|
||||||
categories:
|
|
||||||
- Computer Architecture
|
|
||||||
- Electronics
|
|
||||||
- Hardware
|
|
||||||
tags: [logic-gates, binary]
|
|
||||||
---
|
|
||||||
|
|
||||||
# NAND gate
|
|
||||||
|
|
||||||
A NAND gate is a logic gate that inverts the truth-conditions for `AND`.
|
|
||||||
|
|
||||||
Diagram representing NAND gate:
|
|
||||||
|
|
||||||
<img src="/home/thomas/repos/computer_science/img/NAND.png" width="180" />
|
|
||||||
|
|
||||||
The diagram below shows how the circuit models the truth conditions for `NAND`
|
|
||||||
|
|
||||||
<img src="/home/thomas/repos/computer_science/img/NAND.gif" width="400" />
|
|
||||||
|
|
||||||
- When both switches are off (corresponding to `false` `false`) the output is on (the bulb lights up).
|
|
||||||
- If either one of the switches are on, the output remains on (corresponding to `true` `false` or `false` `true` )
|
|
||||||
- It is only when both switches are on, that the output is off (corresponding to `true` `true` )
|
|
||||||
|
|
||||||
This is the exact opposite to the truth-conditions for AND.
|
|
||||||
|
|
||||||
## Transliterating the logic truth-table to the switch behaviour
|
|
||||||
|
|
||||||
We can now present a truth table for NAND along side that for AND:
|
|
||||||
|
|
||||||
```
|
|
||||||
A B Output
|
|
||||||
_ _ _____
|
|
||||||
|
|
||||||
f f t
|
|
||||||
t f t
|
|
||||||
f t t
|
|
||||||
t t f
|
|
||||||
|
|
||||||
A B Output
|
|
||||||
_ _ _____
|
|
||||||
t t t
|
|
||||||
t f f
|
|
||||||
f t f
|
|
||||||
f f f
|
|
||||||
```
|
|
||||||
|
|
||||||
We can see that it inverts the value of AND.
|
|
||||||
|
|
||||||
## Significance of the NAND gate: functional completeness
|
|
||||||
|
|
||||||
> **Equipped with just a NAND we can represent every other possible logical condition within a circuit.**
|
|
||||||
|
|
||||||
In practice, it is more efficient to use specific dedicated gates (i.e OR, AND, NOT etc) for the other Boolean connectives but in principle the same output can be achieved through NANDs alone.
|
|
||||||
|
|
||||||
When we add more NAND gates and combine them with each other in different ways we can create more complex output sequences and these too will have corresponding truth tables.
|
|
||||||
|
|
@ -1,25 +0,0 @@
|
||||||
---
|
|
||||||
categories:
|
|
||||||
- Computer Architecture
|
|
||||||
- Electronics
|
|
||||||
- Hardware
|
|
||||||
tags: [logic-gates, binary]
|
|
||||||
---
|
|
||||||
|
|
||||||
# OR gate
|
|
||||||
|
|
||||||
> `OR` (in logic known as **disjunction**) in its non-exclusive form is `true` if either of its propositions are `true` or both are `true` . It is `false` otherwise.
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
````
|
|
||||||
p q p v q
|
|
||||||
_ _ _____
|
|
||||||
|
|
||||||
t t t
|
|
||||||
t f t
|
|
||||||
f t t
|
|
||||||
f f f
|
|
||||||
````
|
|
||||||
|
|
||||||
TO DO: Add circuit diagram for OR gate
|
|
||||||
|
|
@ -1,24 +0,0 @@
|
||||||
---
|
|
||||||
categories:
|
|
||||||
- Computer Architecture
|
|
||||||
- Electronics
|
|
||||||
- Hardware
|
|
||||||
tags: [logic-gates, binary]
|
|
||||||
---
|
|
||||||
|
|
||||||
# XOR gate
|
|
||||||
|
|
||||||
> `XOR` stands for **exclusive or**, also known as **exclusive conjunction**. This means it can only be `true` if one of its propositions are `true` . If both are `true` this doesn't exclude one of the propositions so the overall statement has to be `false` . This is the only change in the truth conditions from `OR` .
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
````
|
|
||||||
p q p xv q
|
|
||||||
_ _ ________
|
|
||||||
|
|
||||||
t t f (1)
|
|
||||||
t f t (2)
|
|
||||||
f t t (3)
|
|
||||||
f f f (4)
|
|
||||||
````
|
|
||||||
Loading…
Add table
Reference in a new issue