Last Sync: 2022-08-06 10:30:04

Databases/SQL/1_Language_structure.md

@@ -11,7 +11,7 @@ Before we start using the syntax we need to understand the grammar:
 
 ![](/img/Pasted_image_20220314155028.png)
 
-Expressions differ from clauses and predicates in that they are not the mechanism for returning data (i.e. declaring a clause and a logical condition) they do something to the data, as part of the retrieval. This is a bit subtle: 
+Expressions differ from clauses and predicates in that they are not the mechanism for returning data (i.e. declaring a clause and a logical colllllndition) they do something to the data, as part of the retrieval. This is a bit subtle: 
 
 * `SELECT name FROM model WHERE cores = "4"`
   * This retrieves the models that have 4 cores 

Hardware/Bus.md

@@ -10,7 +10,7 @@ A bus is a communication system that transfers data between components inside a
 ## Main buses 
 
 ### System bus
-The primary pathway between the CPU and [memory](Memory/Basics.md).
+The primary pathway between the CPU and [memory](Memory/Basics.md). It comprises the **data bus**  that transfers data from the memory to the CPU and the **address bus** which transmits requests from the CPU to memory.
 
 ### Internal bus
 Connects local devices for example the harddisk to the CPU.

Hardware/CPU/CPU_architecture.md

@@ -7,6 +7,8 @@ tags:
 
 # CPU architecture
 
+// TO DO: explain about registers
+
 At the core of a computer sits the Central Processing Unit. This is what manages and executes all computation.
 
 The CPU comprises three core components:
@@ -15,8 +17,8 @@ The CPU comprises three core components:
 * the Arithmetic Logic Unit (ALU)
 * the Control Unit (CU)
 
- > 
  > This method of putting together a computer is known as the **Von Neumann Architecture**. It was devised by John von Neumann in about 1945, well before any of the components that would be needed to produce it had actually been invented.
+ 
 
 ## Registers
 

Hardware/Memory/RAM_types.md

@@ -22,7 +22,10 @@ When we think of memory we generally think of the _main_ memory: the 8GB or 16GB
 
 ### SRAM 
 
-SRAM (Static Random Access Memory) is also volatile memory but, in terms of the electronics, it is different in its implementation. In contrast to DRAM it doesn't use capacitors. As a result the transistors do not leak and therefore do not need to be refreshed, hence why SRAM is _static_ and DRAM is _dynamic_. It also uses multiple transistors  per bit. This makes it faster than DRAM but more expensive. DRAM is at least ten times slower than SRAM.
+SRAM (Static Random Access Memory) is also volatile memory but, in terms of the electronics, it is different in its implementation. In contrast to DRAM it doesn't use capacitors. As a result the transistors do not leak and therefore do not need to be refreshed, hence why SRAM is _static_ and DRAM is _dynamic_. It also uses multiple transistors  per bit. This makes it faster than DRAM but more expensive. DRAM is at least ten times slower than SRAM. SRAM is used as [cache memory](/Hardware/Memory/Role_in_computation.md#the-role-of-the-cache) on the [motherboard](/Hardware/Motherboard.md) of which there are two types: L1 (on the processor chip) and L2 (separate from the processor).
+### Relative speeds
+The table below details the relative speeds of the different types of memory and those of other types of motherboard storage.
+
 
 ## References
 

Hardware/Memory/Role_in_computation.md

@@ -11,4 +11,23 @@ The following steps outline the way in which memory interacts with the processor
 1. A file is loaded from the harddisk into memory.
 2. The instruction at the first address is sent to the CPU, travelling accross the data bus part of the [system bus](/Hardware/Bus.md#system-bus).
 3. The CPU processes this instruction and then sends a request accross the address bus part of the system bus for the next instruction to the memory controller within the [chipset](/Hardware/Chipset_and_controllers.md).
-4. The chipset finds where this instruction is stored within the [DRAM](/Hardware/Memory/RAM_types.md#dram) and issues a request to have it read out and send to the CPU over the data bus. 
+4. The chipset finds where this instruction is stored within the [DRAM](/Hardware/Memory/RAM_types.md#dram) and issues a request to have it read out and send to the CPU over the data bus. 
+
+> This is a simplified account; it is not the case that only single requests are passed back and forth. This would be inefficient and time-wasting. The kernel sends to the CPU not just the first instruction in the requested file but also a number of instructions that immediately follow it. 
+
+Every part of the above process - the journey accross the bus, the lookup in the controller, the operations on the DRAM, the journey back accross the bus - takes muliple CPU clock cycles. 
+
+## The role of the cache
+
+The cache is SRAM memory that is separate from the DRAM memory which comprises the main memory. It exists in order to boost perfomance when executing the read/request cycles of the steps detailed above. 
+
+There are two types of cache memory: 
+
+* L1 cache
+  * Situated on the CPU chip itself
+* L2 cache
+  * Situated outside of the CPU on its own chip
+
+The L1 cache is the fastest since the data has less distance to travel when moving to and from the CPU. This said, the L2 cache is still very fast when compared to the main memory, both because it is SRAM rather than DRAM and because it is closer to the processor than the main memory.
+
+Cache controllers use complex algorithms to determine what should go into the cache to facilitate the best performance, but generally they work on the principle that what has been previously used by the CPU will be requested again soon.