From 29b0beddf2f49d3dd46ccc32d50bd587c09d29a8 Mon Sep 17 00:00:00 2001 From: tactonbishop Date: Wed, 30 Nov 2022 07:30:04 +0000 Subject: [PATCH] Last Sync: 2022-11-30 07:30:04 --- .../Digital_Circuits/Half_adder_and_full_adder.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md index 3061481..9821535 100644 --- a/Electronics/Digital_Circuits/Half_adder_and_full_adder.md +++ b/Electronics/Digital_Circuits/Half_adder_and_full_adder.md @@ -86,3 +86,13 @@ And the carry-out bit replicates the truth conditions of [AND](/Hardware/Logic_G | F | F | T | It is therefore possible to implement a half-adder with just these two logic gates: + +The digital circuit above has the same inputs and outputs as the half adder diagram above. + + + +## Full adder + +As the half adder only calculates the least significant bit, it is not sufficient by itself to complete a binary addition; it cannot account for movements in binary place value. To carry out full calculations it must be supplemented with the full adder. + +The full adder takes in three inputs and has two inputs. It is identical to the half-adder apart from the fact that one of its inputs is **carry-in**. This is obviously equivalent to the value that is designated as **carry-out** in a half adder