Last Sync: 2022-08-07 11:00:04

Hardware/Bus.md

@@ -38,7 +38,12 @@ Serial Transmission is the type of transmission in which a single communication
 <img src="../img/parallel-transmission.jpg" width="800px"/>
 
 * Serial buses are cheaper to implement than parallel buses
-* Serial buses are slower than parallel buses
+* Serial buses operate at greater [latency](/Hardware/Bus.md#latency) than parallel buses
+## Latency 
+
+Latency means _delay_: the delay from the time the data is requested until the time it arrives. In the context of a microprocesser and buses a key locus of latency would be between the time a request takes to travel accross the system bus from the CPU to the memory.
+
+// TODO: Add explanation of bandwidth in the context of Hertz
 
 ## Standards
 The mode of transmission is used to distinguish the different bus standards.

Hardware/Memory/Role_in_computation.md

@@ -32,4 +32,4 @@ There are two types of cache memory:
 
 The L1 cache is the fastest since the data has less distance to travel when moving to and from the CPU. This said, the L2 cache is still very fast when compared to the main memory, both because it is SRAM rather than DRAM and because it is closer to the processor than the main memory.
 
-Cache controllers use complex algorithms to determine what should go into the cache to facilitate the best performance, but generally they work on the principle that what has been previously used by the CPU will be requested again soon. 
+Cache controllers use complex algorithms to determine what should go into the cache to facilitate the best performance, but generally they work on the principle that what has been previously used by the CPU will be requested again soon. If the CPU has just asked for an instruction at memory location 555 it's very likely that it will next ask for the one at 556, and after that the one at 557 and so on. The cache's controller circuits therefore go ahead and fetch these from slow DRAM to fast SRAM>