Autosave: 2022-12-10 12:00:05

Computer_Architecture/Bus.md

@@ -15,7 +15,7 @@ A bus is a communication system that transfers data between components inside a
 
 ### System bus
 
-The primary pathway between the CPU and [memory](Memory/Basics.md). It comprises the **data bus** that transfers data from the memory to the CPU and the **address bus** which transmits requests from the CPU to memory.
+The primary pathway between the CPU and [memory](/Computer_Architecture/Memory/Memory.md). It comprises the **data bus** that transfers data from the memory to the CPU and the **address bus** which transmits requests from the CPU to memory.
 
 ### Internal bus
 
@@ -31,7 +31,7 @@ Allows expansion boards to access the CPU and memory.
 
 ### Frontside bus
 
-Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](../Electronics_and_Hardware/Motherboard.md) devices.
+Main computer bus that determines data transfer rate speed and is the primary data transfer path between the CPU, RAM and other [motherboard](Electronics_and_Hardware/Motherboard.md) devices.
 
 ### Backside bus
 
@@ -49,7 +49,7 @@ Serial Transmission is the type of transmission in which a single communication
 <img src="../img/parallel-transmission.jpg" width="800px"/>
 
 - Serial buses are cheaper to implement than parallel buses
-- Serial buses operate at greater [latency](/Hardware/Bus.md#latency) than parallel buses
+- Serial buses operate at greater [latency](/Computer_Architecture/Bus.md#latency) than parallel buses
 
 ## Latency
 

Computer_Architecture/CPU/CPU_architecture.md

@@ -18,9 +18,9 @@ The CPU comprises three core components:
 
 ## Registers
 
-This is the part of the CPU that stores data. The memory cells that comprise it do not have [capacitors](/Hardware/Memory/Memory.md) (unlike RAM) so they cannot store very much data but they work faster, which is what is important.
+This is the part of the CPU that stores data. The memory cells that comprise it do not have [capacitors](/Computer_Architecture/Memory/Memory.md) (unlike RAM) so they cannot store very much data but they work faster, which is what is important.
 
-In terms of speed, registers sit at the top part of the overall [memory hierarchy](/Hardware/Memory/Memory.md#the-memory-hierarchy).
+In terms of speed, registers sit at the top part of the overall [memory hierarchy](/Computer_Architecture/Memory/Memory.md#the-memory-hierarchy).
 
 There are five main types of register in the CPU:
 
@@ -34,7 +34,7 @@ There are five main types of register in the CPU:
 
 ## Arithmetic Logic Unit
 
-This is the hub of the CPU, where the binary calculations occur. It comprises [logic gates](/Hardware/Logic_Gates/Logic_gates.md) that execute the instructions passed from memory. This is where the data stored by the registers is acted upon.
+This is the hub of the CPU, where the binary calculations occur. It comprises [logic gates](/Electronics_and_Hardware/Logic_gates/Logic_gates.md) that execute the instructions passed from memory. This is where the data stored by the registers is acted upon.
 
 It can execute arithmetic on binary numbers and logical operations. This is where you will find operations conducted by adders and half-adders etc.
 
@@ -58,7 +58,7 @@ The CPU's [controller](/Hardware/Chipset_and_controllers.md). It takes the instr
 
 Whilst modern CPUs and multithreading make it appear[] as though the CPU is capable of running multiple processes at once, access to the CPU is in fact sequential. The illusion of simultaneous computation is due to the fact the processor is so fast that we do not detect the sequential changes. For this to happen, the CPU needs to have a means of scheduling and sequencing processes. This is made possible through the system clock, hence when talking about the speed of the CPU we do so with reference to _clock speeds_ and the _clock cycle_.
 
-The clock's circuitry is based on a quartz crystal system like that used in watches. At precisely timed intervals, the clock sends out pulses of electricity that cause bits to move from place to place within [logic gates](/Hardware/Logic_Gates/Logic_gates.md) or between logic gates and [registers](/Computer_Architecture/CPU/CPU_architecture.md#registers).
+The clock's circuitry is based on a quartz crystal system like that used in watches. At precisely timed intervals, the clock sends out pulses of electricity that cause bits to move from place to place within [logic gates](/Electronics_and_Hardware/Logic_Gates/Logic_gates.md) or between logic gates and [registers](/Computer_Architecture/CPU/CPU_architecture.md#registers).
 
 Simple instructions such as add can often be executed in just one clock cycle, whilst complex operations such as divide will require a number of smaller steps, each using one cycle.
 

Computer_Architecture/CPU/Fetch_decode_execute.md

@@ -37,7 +37,7 @@ Once the CPU has received the instruction, the CPU controller chip analyses it t
 ## Execute
 
 Now the command will be executed. The operand is copied to the Memory Address Register and then passed to the Memory Data Register and the command is carried out by the ALU.
-The activities of ALU are covered in [CPU Architecture](/Computer_Architecture/CPU/CPU_architecture.md#arithmetic-logic-unit) and the notes on [Logic Gates](/Hardware/Logic_Gates/Logic_gates.md).
+The activities of ALU are covered in [CPU Architecture](/Computer_Architecture/CPU/CPU_architecture.md#arithmetic-logic-unit) and the notes on [Logic Gates](/Electronics_and_Hardware/Logic_gates/Logic_gates.md).
 
 ## Store
 

Computer_Architecture/Chipset_and_controllers.md

@@ -9,8 +9,8 @@ tags: [motherboard, chipset]
 
 A **controller** is simply a circuit that controls a process. The **chipset** is a combination of controllers placed on the same piece of silicon.
 
-The chipset manages the data flow between the different components that comprise the [motherboard](/Electronics_and_Hardware/Motherboard.md): processor, [memory](/Hardware/Memory/Memory.md), [harddisk](/Operating_Systems/Disks/What_are_disks.md) and peripherals.
+The chipset manages the data flow between the different components that comprise the [motherboard](/Electronics_and_Hardware/Motherboard.md): processor, [memory](/Computer_Architecture/Memory/Memory.md), [harddisk](/Operating_Systems/Disks/What_are_disks.md) and peripherals.
 
-Buses run in and out of the chipset into these key motherboard components. The main chipset is a kind of junction that sits between the memory and CPU through which the [system bus](/Hardware/Bus.md#system-bus) passes.
+Buses run in and out of the chipset into these key motherboard components. The main chipset is a kind of junction that sits between the memory and CPU through which the [system bus](/Computer_Architecture/Bus.md#system-bus) passes.
 
 The chipset is sometimes called the "glue" or "traffic controller" of the motherboard or _an intelligent intersection of buses_.

Computer_Architecture/Memory/Memory.md

@@ -19,13 +19,13 @@ Programs that are executing are loaded into memory because the chips that compri
 
 ### DRAM
 
-When we think of memory we generally think of the _main_ memory: the 8GB or 16GB+ slots of volatile, non-permanent storage that is utilised by the CPU during the runtime of programs. This is DRAM memory: Dynamic Random Access memory. DRAM uses capacitors that lose [charge](/Electronics/Current.md) over time due to leaks. As a result DRAM is memory that needs to be refreshed (recharged) frequently. For this reason and because it only uses one transistor and capacitor per bit, DRAM is the less expensive form of volatile memory.
+When we think of memory we generally think of the _main_ memory: the 8GB or 16GB+ slots of volatile, non-permanent storage that is utilised by the CPU during the runtime of programs. This is DRAM memory: Dynamic Random Access memory. DRAM uses capacitors that lose [charge](/Electronics_and_Hardware/Analogue_circuits/Current.md) over time due to leaks. As a result DRAM is memory that needs to be refreshed (recharged) frequently. For this reason and because it only uses one transistor and capacitor per bit, DRAM is the less expensive form of volatile memory.
 
 // TODO: Add notes in Electronics on capacitors
 
 ### SRAM
 
-SRAM (Static Random Access Memory) is also volatile memory but, in terms of the electronics, it is different in its implementation. In contrast to DRAM it doesn't use capacitors. As a result the transistors do not leak and therefore do not need to be refreshed, hence why SRAM is _static_ and DRAM is _dynamic_. It also uses multiple transistors per bit. This makes it faster than DRAM but more expensive. DRAM is at least ten times slower than SRAM. SRAM is used as [cache memory](/Hardware/Memory/Role_of_memory_in_computation.md#the-role-of-the-cache) on the [motherboard](/Electronics_and_Hardware/Motherboard.md) of which there are two types: L1 (on the processor chip) and L2 (separate from the processor).
+SRAM (Static Random Access Memory) is also volatile memory but, in terms of the electronics, it is different in its implementation. In contrast to DRAM it doesn't use capacitors. As a result the transistors do not leak and therefore do not need to be refreshed, hence why SRAM is _static_ and DRAM is _dynamic_. It also uses multiple transistors per bit. This makes it faster than DRAM but more expensive. DRAM is at least ten times slower than SRAM. SRAM is used as [cache memory](/Computer_Architecture/Memory/Role_of_memory_in_computation.md#the-role-of-the-cache) on the [motherboard](/Electronics_and_Hardware/Motherboard.md) of which there are two types: L1 (on the processor chip) and L2 (separate from the processor).
 
 ### Relative speeds
 

Computer_Architecture/Memory/Role_of_memory_in_computation.md

@@ -10,8 +10,8 @@ The following steps outline the way in which memory interacts with the processor
 
 1. A file is loaded from the harddisk into memory.
 2. The instruction at the first address is sent to the CPU, travelling accross the data bus part of the [system bus](/Hardware/Bus.md#system-bus).
-3. The CPU processes this instruction and then sends a request accross the address bus part of the system bus for the next instruction to the memory controller within the [chipset](/Hardware/Chipset_and_controllers.md).
-4. The chipset finds where this instruction is stored within the [DRAM](/Hardware/Memory/Memory.md#dram) and issues a request to have it read out and send to the CPU over the data bus.
+3. The CPU processes this instruction and then sends a request accross the address bus part of the system bus for the next instruction to the memory controller within the [chipset](/Computer_Architecture/Chipset_and_controllers.md).
+4. The chipset finds where this instruction is stored within the [DRAM](/Computer_Architecture/Memory/Memory.md#dram) and issues a request to have it read out and send to the CPU over the data bus.
 
 > This is a simplified account; it is not the case that only single requests are passed back and forth. This would be inefficient and time-wasting. The kernel sends to the CPU not just the first instruction in the requested file but also a number of instructions that immediately follow it.
 

Electronics_and_Hardware/Analogue_circuits/Cells_and_batteries.md

@@ -6,7 +6,7 @@ tags: [physics, electricity]
 
 # Cells and batteries
 
-Cells are a [voltage source](/Electronics/Voltage.md#chemicals-cells-and-batteries) that generate a difference of potential via a positive and negative electrode separated by an electrolytic solution. The electrolytes pull free electrons from one of the materials which creates a positive charge. The other material gains the free electrons creating a negative charge.
+Cells are a [voltage source](/Electronics_and_Hardware/Analogue_circuits/Voltage.md#chemicals-cells-and-batteries) that generate a difference of potential via a positive and negative electrode separated by an electrolytic solution. The electrolytes pull free electrons from one of the materials which creates a positive charge. The other material gains the free electrons creating a negative charge.
 
 > A battery is a combination of two or more cells.
 
@@ -33,7 +33,7 @@ With series connections we distinguish **series aiding** and **series opposing**
 In the case of **series aiding**, cells are connected one in front of another with the positive terminal connecting to the negative terminal of the other in a line.
 
 In this configuration the same current flows through all the cells; it is not cumulative. We represent this as follow>
-However the voltage is cumulative: it is the _sum_ of the individual cell voltages, represented below as [electrical field](/Electronics/Voltage.md#distinguishing-voltage-from-electric-field):
+However the voltage is cumulative: it is the _sum_ of the individual cell voltages, represented below as [electrical field](/Electronics_and_Hardware/Analogue_circuits/Voltage.md#distinguishing-voltage-from-electric-field):
 
 $$
 E_{T} = E_{1} + E_{2} + E_{3} \\

Electronics_and_Hardware/Analogue_circuits/Circuits.md

@@ -8,7 +8,7 @@ tags: [electricity, electrical-circuits]
 
 An electrical circuit is a set of electrical components connected in such a way that current flows in a loop from a voltage source, through the circuit elements and back to the voltage source.
 
-Below is a basic circuit representing a 9-volt [battery]() with a 10,000$\Omega$ [resistor](/Electronics/Resistance.md) attached accross its terminals. Through the application of [Ohm's Law](/Electronics/Physics_of_electricity/Ohms_Law.md) we can determine that the maximum current will be 0.9 miliamps.
+Below is a basic circuit representing a 9-volt [battery](/Electronics_and_Hardware/Analogue_circuits/Cells_and_batteries.md#cells-and-batteries) with a 10,000$\Omega$ [resistor](/Electronics_and_Hardware/Analogue_circuits/Resistance.md) attached accross its terminals. Through the application of [Ohm's Law](/Electronics/Physics_of_electricity/Ohms_Law.md) we can determine that the maximum current will be 0.9 miliamps.
 
 ![](/img/basic-circuit.png)
 

_scripts/auto_save.sh

@@ -3,12 +3,12 @@
 # This script runs as a cron job in half-hour intervals to automatically commit changes to the remote repository
 
 NOTES_PATH="${HOME}/repos/computer_science"
-SPACE_2_UNDRSCR="${HOME}/repos/bash_scripts/space_to_underscore_filename.sh"
+SPACE_TO_UNDERSCORE="${HOME}/repos/bash_scripts/space_to_underscore_filename.sh"
 
 cd "$NOTES_PATH"
 
 # Loop through directories and convert spaces in filenames to underscores
-source ${SPACE_2_UNDRSCR}
+source ${SPACE_TO_UNDERSCORE}
 git pull
 CHANGES_EXIST="$(git status --porcelain | wc -l)"